1. Technical Field
The present invention relates to a semiconductor memory device, and more particularly to a clock control circuit of a semiconductor memory device.
2. Related Art
In general, a semiconductor memory device includes a clock generation circuit such as a delay locked loop (DLL) circuit or a phase locked loop (PLL) circuit to generate an internal clock having a phase advanced by a predetermined time as compared with that of an external clock. In a semiconductor memory device such as a double data rate synchronous dynamic random access memory (DDR SDRAM), the internal clock output from the clock generation circuit includes a rising clock and a falling clock. The rising clock has a phase to output data at rising edge time of the external clock through a duty cycle correction operation after the internal clock is generated. Further, the falling clock has a phase to output data at falling edge time of the external clock.
A data output buffer provided in the semiconductor memory device alternately buffers rising data and falling data, which are transferred through a global line GIO, in synchronization with the rising clock and the falling clock, and then outputs the rising data and the falling data. When the rising clock has a phase opposite to that of the falling clock, the data output buffer can operate stably. However, since the data output buffer is not adjacent to the clock generation circuit, the phases of the rising and falling clocks are affected by delay devices existing on a transmission path forwarding to the data output buffer.
As illustrated in FIG. 1, if the phase of the rising clock ‘rclk’ is not opposite to the phase of the falling clock ‘fclk’, which are transmitted to the data output buffer, data ‘d_out’ does not have a uniform period. In detail, a data bit synchronized with the falling clock ‘fclk’ may have a shorter output section as compared with a data bit synchronized with the rising clock ‘rclk’. In such a case, the stability may deteriorate in a data output operation. If such phenomenon becomes more pronounced, data synchronized with the falling clock ‘fclk’ may not be output, so that distorted data may be output.
As described above, in order to stably perform a data output operation in the semiconductor memory device, the phase of the rising clock must be opposite to the phase of the falling clock, which is transmitted to the data output buffer. However, according to the related art, the rising and falling clocks having distorted phases are transmitted to the data output buffer due to delay devices existing on a transmission path between the clock generation circuit and the data output buffer, so that stability of the data output operation may deteriorate. In this regard, a method for stably transmitting a clock is required to improve reliability of the data output operation.